India is actively strengthening its position in the global semiconductor landscape by investing heavily in chip design capabilities. The Chips to Start-up (C2S) Programme, launched by the Ministry of Electronics and Information Technology (MeitY) in 2022, is a central part of this effort. With the global semiconductor market projected to approach USD 1 trillion by 2030 and a worldwide shortage of over 1 million skilled professionals expected by 2032, India is seizing the opportunity to build indigenous expertise in a sector where it already has significant strength.
Why Chip Design Is Strategic for India
Semiconductors are the backbone of modern electronics, artificial intelligence, national security systems, automobiles, telecom networks, and consumer devices. While India has long excelled in chip design services for global companies, the country has relied almost entirely on foreign foundries for fabrication. The C2S Programme changes this by enabling students, researchers, and startups to design, verify, fabricate, and test their own chips and intellectual property. This focus on indigenous design capability is a crucial step toward technological self-reliance and long-term global competitiveness.
Core Objectives and Ambitious Targets
The programme operates with a total outlay of ₹250 crore over five years and aims to develop 85,000 industry-ready professionals across different academic levels. Its targets include training 200 PhD scholars in advanced chip design research, producing 7,000 M.Tech graduates specialising in VLSI or embedded systems, equipping 8,800 M.Tech graduates from related streams with focused VLSI exposure, and reaching 69,000 B.Tech students through VLSI-oriented coursework.
Beyond manpower development, C2S pursues tangible outcomes: it aims to incubate 25 startups, facilitate 10 technology transfers, train 1 lakh students overall, generate at least 50 patents, and support more than 2,000 high-quality research publications.
End-to-End Hands-on Training Ecosystem
Participants receive practical, real-world exposure across the entire chip design lifecycle—from concept and simulation through fabrication and silicon validation. The programme provides access to industry-standard Electronic Design Automation (EDA) tools from Synopsys, Cadence, Siemens EDA, Ansys, Keysight, Silvaco, AMD, and Renesas, along with high-performance computing resources, IP libraries, FPGA prototyping boards, and supercomputing power via PARAM Utkarsh.
The ChipIN Centre at C-DAC Bengaluru functions as the national hub. It provides shared infrastructure, continuous technical mentorship, design verification services, and organises quarterly shared wafer runs. Student and researcher designs are collected, checked for compliance, aggregated onto multi-project wafers, fabricated at the Semi-Conductor Laboratory (SCL) in Mohali using 180 nm technology, packaged, and returned for testing and evaluation. The SMART Lab at NIELIT Calicut complements this ecosystem by offering short-term certification courses and additional hands-on facilities. Together, these mechanisms currently serve more than 400 organisations, including 305 academic institutions and 95 startups, ensuring wide and inclusive participation across India.
Impressive Results Achieved So Far
The programme has already shown strong, measurable impact. Over 1 lakh individuals have enrolled in chip design training, with approximately 67,000 trained to date. The ChipIN Centre has completed six shared wafer runs at SCL Mohali, resulting in 122 chip design submissions from 46 institutions and the successful fabrication, packaging, and delivery of 56 student-designed chips.
More than 265 industry-led training sessions have taken place, while participating institutions have filed over 75 patents and are actively developing more than 500 IP cores, ASICs, and SoC designs targeting critical sectors such as defence, telecom, automotive, consumer electronics, and industrial applications. Users have collectively logged over 175 lakh hours on shared national EDA infrastructure, and the ChipIN Centre has successfully resolved more than 4,855 technical support requests from participants.
Coordinated Institutional Framework
MeitY provides overall policy leadership, funding, and programme oversight. C-DAC operates the ChipIN Centre as the central design enablement platform. SCL Mohali executes fabrication and packaging using established process technologies. This tightly integrated structure promotes strong academia-industry collaboration, ensures equitable access to advanced tools and facilities, and continuously builds a reliable pipeline of skilled chip designers.
The Bigger Picture
The Chips to Start-up Programme goes beyond traditional skill-development initiatives. It actively cultivates a self-sustaining indigenous semiconductor design ecosystem by integrating large-scale training, hands-on fabrication experience, patent generation, startup incubation, and shared national infrastructure. These efforts equip India’s engineers, researchers, and entrepreneurs to create original chips, IP, and technologies—positioning the country to contribute meaningfully to the global semiconductor value chain and secure strategic independence in an era increasingly defined by electronics, AI, and advanced computing.
